1. Field of the Invention
This disclosure relates to a semiconductor memory device and a method of operating the same, and more particularly, to a memory device capable of retaining data when an internal voltage generator does not operate, and a method of operating the same.
2. Description of the Related Art
There is a growing need for low-power memories in mobile devices, such as personal digital assistants (PDA) and notebook computers. Such devices are being used ever more widely. To satisfy the need, a method of reducing power consumption by adjusting a refresh cycle based on how the length of time data is retained in a memory cell changes according to temperature, and a low-power dynamic random access memory (DRAM) with a partial refresh function that refreshes only a desired part of the DRAM, have been proposed.
A power-down mode in which a memory device in an active/standby state operates to reduce power consumption has been proposed in the Joint Electronic Device Engineering Council (JEDEC). Also, the standard for a deep power-down mode (hereinafter referred to as “DPD mode”) in which power consumption is minimized by not operating an internal voltage generator in a memory device when the memory device is not used, is specified in the JEDEC.
FIG. 1 is a timing diagram of the DPD mode specified in the JEDEC. Referring to FIG. 1, a memory device enters the DPD mode in synchronization with a clock signal CLK when a clock enable signal CKE, a write enable signal /WE, and a selection signal /CS are at a logic low level and a row address strobe signal /RAS and a column address strobe signal /CAS are at a logic high level; and exits the DPD mode when the clock enable signal CKE is at a logic high level.
After exiting the DPD mode, the memory device normally operates after a predetermined period of time, e.g., a power-up sequence of 200 us. During the DPD mode, all internal voltage generators in the memory device are disabled, that is, they do not operate, thereby reducing power consumption.
Although, power consumption is low in the DPD mode illustrated in FIG. 1, data stored in memory cells of the memory device is not retained. This is because the internal voltage generators do not operate, and thus, a refresh operation cannot be performed. Therefore, in a conventional memory device, to retain the data, during the DPD mode, before entering the DPD mode, data stored in the memory device must be moved to another storage location.